Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions 1 2 3 12 I , I , I ,......I is executed in this pipelined
processor. Instruction 4 I is the only branch instruction and its branch target is 9 I . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

Option
(A) 132
(B) 165
(C) 176
(D) 328

• RAM chip size = 1k × 8
  1024 words of 8 bits each 
  RAM to construct =16k × 16
  Number of chips required = (16k * 16) / (1k * 8) = 32 = 16 * 2 [16 chips vertically with each
  having 2 chips horizontally]
  So to select one chip out of 16 vertical chips, we need 4 x 16 decoder.
  Available decoder is – 2 x 4 decoder
  To be constructed is 4 x 16 decoder Therefore to construct 4 x 16 decoder using 2 x 4 decoders, you will need Five 2 x 4 decoders.
• 10 years agoHelpfull: Yes(0) No(1)