Gate Exam

Suppose a circular queue of capacity ( n-1) elements is implemented with an array of n elements.
Assume that the insertion and deletion operations are carried out using REAR and FRONT as array
index variables, respectively. Initially, REAR = FRONT = 0. The conditions to detect queue full
and queue empty are

option
(A) full: (REAR+1) mod n == FRONT
empty: REAR == FRONT

(B) full: (REAR+1) mod n == FRONT
empty: (FRONT+1) mod n == REAR

(C) full: REAR == FRONT
empty: (REAR+1) mod n == FRONT

(D) full: (FRONT+1) mod n == REAR
empty: REAR == FRONT

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Gate Other Question

An Internet Service Provider (ISP) has the following chunk of CIDR -based IP addresses available with it: 245.248.128.0/20. The ISP wants to give half of this chunk of addresses to Organization A, and a quarter to Organization B, while retaining the remaining with itself. Which of the following is a valid allocation of addresses to A and B?

option
(A) 245.248.136.0/21 and 245.248.128.0/22
(B) 245.248.128.0/21 and 245.248.128.0/22
(C) 245.248.132.0/22 and 245.248.132.0/21
(D) 245.248.136.0/24 and 245.248.132.0/21
Let G be a complete undirected graph on 6 vertices. If vertices of G are labeled, then the number of distinct cycles of length 4 in G is equal to

option
(A) 15
(B) 30
(C) 90
(D) 360