Gate Exam

An application loads 100 libraries at startup. Loading each library requires exactly
one disk access. The seek time of the disk to a random location is given as 10ms.
Rotational speed of disk is 6000rpm. If all 100 libraries are loaded from random
locations on the disk, how long does it take to load all libraries? (The time to
transfer data from the disk block once the head has been positioned at the start
of the block may be neglected)

option
(A) 0.50s
(B) 1.50s
(C) 1.25s
(D) 1.00s

Read Solution (Total 1)

disk access time =seek time +rotational latency+transfer time (given that transfer time is neglected)

here seek time=10msec

rotational speed=6000rpm

60sec ----- 6000 rotation

1 rotation------60/6000 sec

rotational latency---1/2 *60/6000 sec=5msec

total time to transfer one library=10+5=15 msec

total time to transfer 100 libraries=100*15msec=1.5 sec
9 years agoHelpfull: Yes(0) No(0)

Gate Other Question

An 8KB direct mapped write-back cache is organized as multiple blocks, each of
size 32-bytes. The processor generates 32-bit addresses. The cache controller
maintains the tag information for each cache block comprising of the following.
1 Valid bit
1 Modified bit
As many bits as the minimum needed to identify the memory block mapped in
the cache.
What is the total size of memory needed at the cache controller to store metadata
(tags) for the cache?

option
(A) 4864 bits
(B) 6144 bits
(C) 6656 bits
(D) 5376 bits On a non-pipe lined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500 LOOP:
Load a byte from device Store in memory at address given by address register
Increment the address register Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine
instruction which takes one clock cycle to execute if it is a non-load/store
instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA
controller to implement the same transfer. The DMA controller requires 20 clock
cycles for initialization and other overheads. Each DMA transfer cycle takes two
clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used
in place of the interrupt driven program based input-output?
option
(A) 3.4
(B) 4.4
(C) 5.1
(D) 6.7