Gate Exam

Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
option
(A) Immediate Addressing
(B) Register Addressing
(C) Register Indirect Scaled Addressing
(D) Base Indexed Addressing

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Gate Other Question
Let the page fault service time be 10ms in a computer with average memory access time being 20ns. If one page fault is generated for every 10^6 memory accesses, what is the effective access time for the memory?
option
(A) 21ns
(B) 30ns
(C) 23ns
(D) 35ns In a compiler, keywords of a language are recognized during option
(A) parsing of the program
(B) the code generation
(C) the lexical analysis of the program
(D) dataflow analysis